Using SPICE model blocks – Part Three

­This article is Part Three of a mini-series, presenting useful SPICE model blocks to help motor control and power supply designers perform effective simulations.  Part Two introduced a block called “CLOCKDRIVER” (see PSD, May 2017) for driving half-bridge circuits.  CLOCKDRIVER converts one reference input clock to two, differential, floating, out-of-phase clocks, with programmable deadtime, and slew-rate control.  Review Part One-DUALCLOCK, which is much simpler, with faster analysis times.  Both blocks utilized math functions hidden in the SPICE Model. 

After receiving several requests, and searching online for hardware implementation of this function,  decided to design and publish a simple circuit for generating two asynchronous clocks with adjustable deadtime. There are several complex methods online, but nothing this simple, and none offered SPICE models .  ASYNC_CLOCK model  outputs are single-ended, with no enable function.  Typically, these clocks feed into half-bridge drivers, such as AOZ32101MDV (Alpha & Omega Semiconductor) used in this example.  Driver-ICs will handle high-side gate drive, support enable, and floating differential outputs. With the addition of proper building blocks, using traditional SPICE tools (such as Multisim by National Instruments)to simulate power supplies becomes much easier.  For those of us that love to simulate, we know what a joy it is when a “block” or SPICE model is fully tested and available, ready to drop into our schematic so that we can continue to work on the circuit at hand, to solve and analyze our immediate needs.  Without these tested blocks, we waste time troubleshooting models instead of designing circuits.  Hardware design is provided below, to implement in the real world.  ASYNC_CLOCK presented here is another model that will converge cleanly, run quickly, and has been tested and proven.   

ASYNC_CLOCK can be utilized for finding optimum operating frequency of synchronous buck converters or DC motor circuits, see typical application circuit (Figure 1) Basic DC Motor control application with simplified output stage.   20kHz clock source shown can be replaced by function generator.  Output is a voltage, level controlled by the duty cycle of the clock input (CLK).  Computer-aided design using this block will help select values for the output stages.  Simulating inverter waveforms takes a lot of computing horsepower, so please be patient with your simulation tools.  Slewrate (in this model) is controlled by the rise and fall times of the logic gates utilized. 

ASYN_CLOCK creates two out-of-phase, differential, single-ended clock outputs, with programmable slewrate and deadtime, from a single-ended input clock.  Duty cycle is controlled by the input clock.  Enable can be added with additional logic, but normally controlled by the driver.  DEADTIME(ns) parameter is controlled by C_delay (capacitor value in pF).  Equation DEADTIME=(1.34 x C_delay) + 27.5, is embedded in the parameters section of the model.  For hardware implementation (set R_delay to 2kΩ), the equation is approximately true for deadtime up to 1µs.  ASYNC_CLOCK has been written to run efficiently in SPICE, however, care should be taken to fully understand the threshold points and timing diagram.  There is a propagation delay through the block, related to the delay through the logic gates, not including DEADTIME value.  Default is set to 5ns.  Determine and understand the switching thresholds required for your application.  There is also nominal duty cycle or phase distortion caused by RISETIME and FALLTIME variables.  For most simulation circuits, this will introduce very small error terms in timing.  DEADTIME guarantees no shoot-through conditions, since both outputs are held LOW before either signal switches HIGH.  Logic threshold voltages are adjustable, set to 2.5V by default.  This parameter will vary with various logic families (LV, LVC, AC, HC, HCT, TTL, etc.).  For more precise simulations, please embed the (readily available) exact model from the correct logic family.   

Figure 2 shows the simple schematic and symbol for ASYNC_CLOCK.  The concept is simple, but following the SPICE syntax becomes complex rather quickly.  Basically, the incoming clock (CLK) is split into in-phase and slightly-delayed signals.  High-side output is TRUE when the delayed signal and original CLK are both HIGH.  Low-side output is TRUE when the delayed signal and original CLK are both LOW.  Since the outputs are defined as “digital” by most SPICE engines, series resistance was inserted to create an analog voltage.  By convention, this model keeps the high-side output (HS) in-phase and the low-side output (LS) out-of-phase with the reference clock input.  Duty cycle is completely controlled by the input clock (CLK), consistent with Synchronous Rectification circuits, such as the Synchronous Buck Regulator.   For example, 10% percent duty cycle for the input clock would drive the low-side n-channel MOSFET HIGH, 90% of the time. 

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Figure 2:  ASYNC_CLOCK Schematic & Symbol

Figure 3 provides source code for the SPICE model.   This model was written for National Instruments Multisim v14, and some syntax may require modification to use with other SPICE tools.

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Figure 3:  SPICE Model for ASYNC_CLOCK

The timing diagram of Figure 4 shows relative timing of all edges for input clock (CLK) and two outputs (HS & LS).  Each cycle starts with input clock (CLK) rising above the threshold voltage (set to 2.5V).  LS output starts dropping to zero, after the propagation delay through the model.  Both outputs remain low for the DEADTIME time interval.  HS output will begin to rise at the end of DEADTIME.  HS remains high until CLK goes low.  After HS goes to zero, DEADTIME is inserted and finally LS output goes high.  Period ends with CLK rising high.

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Figure 4:  ASYNC_CLOCK Timing Diagram

The deadtime interval is critically important between the switching cycles, as it eliminates possible shoot-through conditions, (when both MOSFETs are conducting simultaneously) in any full-bridge, half-bridge, PWM, Three-phase Brushless Motor, High-Current Transducer Drive, Switched Mode Power Supply, or other circuits that implement synchronous rectification.  To improve duty cycle accuracy, your input clock should have fast edges relative to the rise/fall times of the logic gates. 

Analyzing motor control or power supply circuits with SPICE is never simple.  Expect convergence errors and long analysis times, that never seem to end.   Keep in mind, that similar to real circuits, the analysis is performing EXACTLY the task that you requested, but possible not the task that you had intended.  Results are mathematical calculations.  Nothing more.  SPICE circuits are not real, they are simple illusions.  Read that sentence again.  Strange inputs will yield strange results.

Additional articles will explore some useful test cases utilizing this model and others featured in the mini-series.  Simulation results correlated very well with actually laboratory testing.  Procedures will later be presented explaining test and simulation methods for identifying shoot-through conditions in synchronous buck designs.  Model text files are available upon request.  Keep simulating and always have fun.

Alpha & Omega Semiconductor