Ultralow Power High Speed ADC

High Speed ADCs are integral to low power applications such as wireless communication, medical instrumentation and data acquisition systems. Speed requirements of the ADCs vary from a few kHz to GHz, and resolution varies from 6bit to 24bit depending on application. High speed ADC in low power applications Multiple architectures are used to implement ADCs with wide variety of speed/resolution combination and applications. Battery operated wireless products require ultra low power consumption to increase battery discharge time and longer battery life. The number of parallel analog channels in medical instrumentation and data acquisition systems can be maximized by the use of low power high speed ADCs. Hence, the reduction of power consumption of high speed ADCs is becoming critical for the electronics industry. ADCs with 10bits to 12bits resolution operating at 100MHz sample rates are most commonly used in a wide range of low power applications. To satisfy such requirements, an 11bit 100MHz ADC was developed in 65nm CMOS technology which consumes only 1.2mW from a 1.2V supply. Pipelined ADCs are most suitable for achieving such speed and resolution, and the main contributor of consumption in pipelined ADCs is the operational amplifier (op amp). The challenge High speed ADCs realized with 1.5bits per stage and single stage op amps are traditionally considered to be the most power optimal architecture in this category. In this architecture the maximum bandwidth of op amps is scaled down by a factor of 2 only in closed loop configuration and thus half of the bandwidth can be utilized. Also, this architecture uses a minimum number of comparators and offers very high tolerance for comparator offset. If the number of bits per stage is increased, say to 2.5bits per stage, the required number of op amps is less. But the available bandwidth of the operational amplifiers is scaled down by a factor of 4 in closed loop configuration of 2.5bit architecture implementation. Hence the available bandwidth is actually half of what is available in 1.5bits stage. To regain the similar bandwidth, each op amp has to be biased with more than double the bias current. In addition to that, the numbers of comparators are also increased in this architecture. Thus, 2.5bits per stage architecture does not offer any power advantage over 1.5bits per stage if both are implemented using traditional single stage op amps. Lowest power high speed ADC available According to papers published in top technical journals and conferences, the lowest power and best known 10bit ADC consumes 4.5mW and is implemented using 1.5bits per stage with a single stage telescopic cascade op amp. 4.5mW was outstanding for ADCs with 10bit resolution and 100MHz speed, but low power needs are gradually becoming more and more demanding, requiring further reduction of power to a bare minimum to gain a substantial competitive edge in this challenging market. Our approach for ultra low power ADC To achieve this target, 2.5bits per stage architecture was revisited. Going back to the basic architectural issue, it was seen that 2.5bits per stage uses half the number of amplifiers, but its limitation is the reduction of the op amp bandwidth by a factor of 4. If bandwidth of the op amp can be retrieved, 2.5bits per stage would be more power optimal. An innovative technique was required to eliminate this particular challenge. The solution The first level of power reduction is achieved by sharing op amps between consecutive stages. In traditional implementations, each stage uses a dedicated op amp. But this amplifier is active in just one phase and inactive in other reset phases. In this design the op amp is shared between two consecutive pipelined stages working in two different clock phases and never remains idle or inactive. After sharing the amplifiers and achieving a factor of power reduction, the focus was shifted to the op amp. A two stage op amp is considered rather than a traditional single stage amplifier to address the bandwidth reduction aspect. Bandwidth and stability margins of single stage op amps are normally governed by the load capacitance present at their output terminals. Moreover, common mode loop stability requires the differential loop to be stable at unity gain, even though the feedback factor of 2.5bits stage requires stability at 12dB gain frequency. So when the op amp is used in 2.5bits stage, the bandwidth is simply reduced by a factor of 4.

To overcome this limitation, a two stage op amp was used, as shown in figure 1, composed of a telescopic cascode followed by a differential gain stage. The telescopic cascode stage need not sustain high signal swing at its output and hence its biasing requirement is not very stringent. The second stage is a simple differential gain stage and can achieve 1.4Vpp-diff swing at a supply voltage up to 1V. Two gain stages have independent common mode controls and this configuration makes the differential loop almost independent of common mode loops. The differential loop can be separately compensated without impacting the common mode loops. Since in 2.5bits per stage architecture the op amp is always used with a feedback factor of 1/4, the op amp needs to be stable with adequate phase/gain margin only at 12dB and not at 0dB gain. On the other hand the available bandwidth of the op amp is also at 12dB gain frequency. In this op amp, the Miller compensation technique was used, which attains necessary stability margins of differential loop at 12dB gain frequency and maximizes the available bandwidth by maintaining the common mode loops stability. This technique is instrumental in reducing the power consumption and hence the overall ADC.

The ADC area is 0.05mm2 with a dimension of 140ux350u. Figure 2 shows dynamic results with sampling frequency variation at 10MHz input. ENOB is 10.08 at 50Msps and 9.91 at 100Msps. Also static results (INL, DNL) and ENOB results are shown.

Abbreviations:

• DNL: Differential Non Linearity, INL: Integral Non Linearity
• SNDR or SINAD: Signal to Noise and Distortion Ratio
• THD: Total Harmonic Distortion
• SFDR: Spurious Free Dynamic Range, ENOB: Effective No of Bits

  Resolution 11Bits Sampling Rate 100Msps Input Dynamic 1.4 Vpp-diff SNDR 59.3dB @ 100Msps/51Mhz Fin Area 140uX350u ( 0.049um2) Technology 65nm FOM comparison and performance summary The ADC consumes total 1.2mW from 1.2V supply resulting in a Figure of Merit (FOM) of 15.6fJ/step. FOM is defined as Power/2^ENOB*2*Band Width. The FOM achieved by this ADC is the best reported so far. Summary Using 2.5bit architecture and a two point approach (i.e. sharing op amps between consecutive stages and an innovative two stage amplifier employing independent common mode loops for each stage) eliminates the 2.5bits per stage bandwidth reduction issue and makes the architecture most power optimal. In this way, the ADC is made of only two op amps, which consume 400uA and 150uA respectively, so the DC power consumption of the core ADC is only 550uA. The remaining power is contributed by switching current. www.st.com