TLVR High Voltage Considerations

Since TLVR is a relatively new development, particular details and properties are still being studied. This article focuses on the transient behavior of TLVR, which affects isolation requirements for the magnetics, as well as isolation and safety considerations for the whole motherboard.

TLVR and Transient

The schematic of TLVR, shown in Fig.1, is used in multi-phase buck regulators. While the main inductor windings are still connected between switching nodes of the phases and Vo, the added auxiliary windings are electrically connected in series to each other and the tuning inductor, L_C. Removing L_C returns the circuit to just discrete inductors in the buck converter. Shorting L_C implies the strongest linking between the phases, as well as the fastest transient performance, but it degrades the current ripple and efficiency.

A potential concern during TLVR transient is the fact that all auxiliary windings are connected in series, with a typical 1:1 transformer ratio-to-primary windings. As the buck phases are typically enabled to align during the transient to improve performance: voltage pulses on the secondary side will align as well.

Consider aggressive loading transient in a 12V to 1.8V application, where all high-side FETs in all phases turn on as fast as possible, so the (V_IN - V_O) = 10.2V voltage is simultaneously applied to all main windings as shown in Fig.2. In the worst case, all 1:1 transformers would generate 10.2V on their secondaries so the resulting voltage pulse on the secondary side would be (V_IN - Vo) ×N_PH. This is clearly a concern for safety. Fig. 2 has some typical ballpark values for the TLVR, the small leakage between the main and auxiliary windings was measured as 5nH.

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Figure 2: An equivalent schematic of TLVR = 150nH with a worst-case loading transient

 

Fig. 3 shows simulations for N_PH = 20 when all V_X switching nodes have a 100ns pulse of 10.2V. All secondary TLVR voltages are plotted to show how a series connection of the windings builds up the voltages. When the secondary windings of 20 linked phases are loaded with L_C = 160nH a) – the voltages on the board reach ~123V. But if L_C is disconnected b), the voltage step can be as high as 197V. The total voltage is closer to the worst case (V_IN - Vo) ×N_PH.

However, the results in Fig. 3 are still too optimistic. In reality, the simplified simulation in Fig. 3 needs to add at least parasitics capacitances between the GND plane and fairly wide traces that connect secondary TLVR windings, on the order of 5pF. Related schematic in Fig. 4 leads to the simulations shown in Fig. 5. Capacitors result in a lot of oscillations in the high-Q circuit. The same N_PH = 20 case shows a voltage peak of 239V when L_C = 160nH is present, and 390V, if L_C is broken off the board.

Notice that the value of the parasitic layout capacitors does not really matter – it only affects the frequency and envelope of oscillations, but not the amplitude.

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Figure 3: TLVR worst-case transient simulation with a) L_C = 160nH, b) L_C is open, N_PH = 20

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Figure 4: Layout capacitances are added to the TLVR equivalent transient schematic

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Figure 5: TLVR worst-case transient simulation with 5pF per secondary node added, a) L_C = 160nH, b) L_C is open, N_PH=20

 

One approach to mitigate this is to make sure that phases cannot align during the transient, but it would clearly put a limit on the transient response. Another approach is to limit the number of linked TLVR phases. But what are the practical limits of this approach, as N_PH needs to be high enough for current ripple impact to be small for efficiency, while N_PH also needs to be low enough to limit worst-case secondary voltage?

Considerations for Linked Nph

Fig. 6 compares normalized current ripple for a coupled inductor and for TLVR as a function of Vo (for V_IN = 12V). Starting with a discrete inductor L (red curve), different number of Nph are either a) magnetically coupled as a single coupled inductor or b) electrically linked as TLVR. Assumptions used:  TLVR = 150nH with leakage 5nH, L_C = 120nH. Coupling ratio L_M/L_K = 5 is assumed for CL. Depending on N_PH, the magnetically coupled inductor significantly reduces current ripple from a discrete inductor with the same value L. The TLVR current ripple, on the other hand, is always larger than in a discrete inductor with the same value L. The TLVR current ripple also has notches at the D = k/N_PH areas. Increasing the number of linked phases is clearly beneficial in decreasing the TLVR current ripple (Fig. 6b).

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Figure 6: Calculated normalized current ripple for different N_PH as a function of Vo (V_IN = 12V) in a) coupled inductor (L_M/L_K = 5) and b) TLVR = 150nH (L_C = 120nH)

 

Fig. 7 shows current ripple as a function of linked N_PH for TLVR = 150nH and different values of L_C. Lower L_C values introduce larger error, but the trends are very clear: lowering N_PH or decreasing L_C leads to an increase in current ripple. Notice that TLVR always has a larger ripple than a “baseline discrete inductor” (L_C = open). It can be concluded that the minimum number of linked phases should be around N_PH_min~1/D, to keep the current ripple impact under control. In other words, increase N_PH at least up to the first notch in the current ripple curve where duty cycles of different phases get close to overlapping.

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Figure 7: Calculated current ripple in TLVR = 150nH for different L_C as a function of linked N_PH (V_IN = 12V, Vo = 1.8V, f_S = 400kHz)

 

Another conclusion is that the minimum desirable number of linked phases will increase with lower Vo as in (1).For V_IN = 12V and Vo = 1.8V, the TLVR solution roughly needs N_PH_min~6, while for Vo = 0.8V it would be N_PH_min~15, see Fig.8. Of course, a smaller number of N_PH is acceptable if some extra impact on current ripple and therefore efficiency is tolerated.

Assuming 12V to 1.8V applications, linking N_PH = 6 is targeted to keep the TLVR current ripple down. Fig.9 shows the secondary TLVR voltage when all phases on primary have a 100ns pulse (V_IN - Vo).  When L_C = 120nH is present, the voltage on the secondary can reach 77V. If L_C is broken off the PCB, the unloaded secondary voltage can oscillate up to 113V.

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Figure 8: Calculated current ripple in TLVR = 150nH for different L_C as a function of linked N_PH.  V_IN = 12V, Vo = 0.8V, fs = 400kHz

 

A rough estimate for the worst-case secondary TLVR voltage would be as shown in (2), where the 2x multiplier is coming from the oscillation instead of a pulse waveform.

Correspondingly, the estimated V_PEAK would be 408V for N_PH = 20 and 122V for N_PH = 6, compared to the simulated 377V (Fig. 5b) and 113V (Fig. 8b), respectively.

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Figure 9: TLVR worst-case transient simulation with 5pF per secondary node added, a) L_C = 120nH b) L_C is open, N_PH = 6

 

Then the estimated N_PH_max to keep the worst-case secondary voltage under the desired minimum V_PEAK could roughly be as shown as (3). Assuming a 60V maximum voltage rating, a 12V to 1.8V application would have N_PH_max < 2.9 and for a 12V to 0.8V application, N_PH_max < 2.6. This creates a problem with keeping the current ripple contained, because of N_PH_min = 6 and N_PH_min = 15 for Vo = 1.8V and Vo = 0.8V, respectively. If a safety rating requires a low enough voltage limit, then it seems that in practical applications, an extra current ripple increase would occur and therefore a more noticeable efficiency impact is expected.

Fig. 10 shows N_PH_min (efficiency) and N_PH_max (safety) as a function of Vo, assuming a safety rating of V_PEAK = 60V and V_IN = 12V. A possible solution between N_PH_min and N_PH_max exists only above Vo = 3.5V, but N_PH_max overrides it at lower voltages due to safety concerns, which leads to higher current ripple and related efficiency impact.

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Figure 10: N_PH_min (efficiency) and N_PH_max (safety) as a function of Vo, assuming V_IN = 12V and a safety rating of V_PEAK = 60V

 

Of course, if N_PH is lowered, this also leads to an increase of the total number of added tuning inductors, L_C, since each linked group needs one.

Conclusion

The TLVR approach is an improvement from a discrete inductor, but it mainly improves the transient while making a current ripple and therefore makes efficiency worse. To keep current ripple impact under control, linking N_PH_min > V_IN/Vo could be recommended. From the safety perspective, if the V_PEAK limit for the worst-case voltage on the PCB is desired, then linking no more than N_PH_max < V_PEAK/((V_IN - Vo) ×2) phases is needed. Safety standards would generally override the current ripple considerations, so a hit in current ripple impact and efficiency in the TLVR approach is to be expected.

The other possibility to mitigate high voltage concerns is to ensure that the controller never aligns more than some maximum number of phases, according to N_PH_max described above (2 to 3 phases max for 60V limit, etc.) The challenge with this approach is that it would limit how fast the system transient performance can be. Overlapping too many phases in steady-state operation should also be considered.

Maxim