Ethernet it is now emerging as the replacement of choice for device-layer fieldbus technologies, having already been widely adopted for industrial control and automation networking. This shift is actively enabling the advent of the Industrial Internet of Things (IIoT) as it offers unparalleled benefits to the industry by remotely identifying, monitoring and controlling every individual device on a network. Management efficiency is drastically improved. This reduces operating costs, but also significantly reduces or even eliminates the risk of machine failure.
To achieve such benefits, Ethernet technology must still evolve to meet industry requirements. One such approach is Micrel's family of 10/100BASE-TX Ethernet PHY Transceivers. The KSZ8061 PHY family delivers market-leading robust performance alongside a number of unique feature attributes. This combination enhances Ethernet's ability to perform at device and sensor layers. This paper outlines some of the key considerations when designing with Ethernet PHY, using the KSZ8061 PHY as an example.
Reducing Power Demands
It is becoming more common on Ethernet PHY devices to support IEEE 802.3az Energy Efficient Ethernet (EEE) standards. This means that when no traffic is sent (idle periods) the PHY can transition into a low power sleep mode. This reduces power consumption by over 50 percent. However, such approaches, in addition to full power down modes, consume an order of mA of current, which still renders it unsuitable for any battery or battery back-up application. To overcome this, The KSZ8061 Ethernet PHY has introduced Ultra Deep Sleep, to achieve an undisputed best of class, standby current of less than 1 μA.
Additionally, the KSZ8061 PHY exhibits a Signal Detect output pin; to signify the presence of an active link partner. The Ultra Deep Sleep – or PHY standby – mode can be activated and woken up automatically by the signal detection circuitry. Furthermore, this output signal can then be employed by the power management to power down the processor and sensors, providing remote sub 1uA standby and wakeup of any remote module.
There are many key advantages to using a physical layer signal detect remote power down scheme relative to other proposed methods that use special waveforms or pattern sequences.
These include:
•Reduced standby power by implementing a detection circuit at the physical layer. This requires less signal processing and therefore, consumes less power.
•Full interoperability with any Ethernet vendor link partner PHY (at ECU). This is an advantage because the use of special waveforms / sequences tends to require proprietary implementation, restricting the practical use.
Enhanced EMC and Reduced Cable Cost are Key Benefits
In the KSZ8061 PHY, fully programmable, integrated noise filtering to reduce emissions and enhance immunity is achieved using Quiet-WIRE technology. This is a unique feature that enables designers to meet automotive and industrial EMC standards while operating over low cost unshielded twisted pair cable, as demonstrated in Figures 1 and 2. Figure 1 compares transceiver line RF emissions based on the IEC61967 standard between a typical Ethernet and the KSZ8061 PHY utilizing Quiet-WIRE technology. What we see is that there is an up to 20dB reduction at frequency range 30MHz and above, all without compromising on cable reach of 130m or more.
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Figure 1. Remote signal detect wake-up and standby in a sensor module example case
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Figure 2. Line emissions are reduced with Quiet-WIRE
Another benefit is that Quiet-WIRE technology also significantly enhances receiver immunity to deliver error free in the most stringent noise environments, again over low cost unshielded cable. We see this in Figure 2, which demonstrates the behavior of a typical Ethernet PHY using the IEC62132 direct power injection (DPI) Immunity method. Errors occurring in the frequency band 10MHz to 250MHz are observed, reducing receiver immunity tolerance by up to 10dBm. However, the KSZ8061 PHY delivers error-free performance in the presence of maximum 39dBm noise injection, across the full frequency range.
Improving Reliability and Fault Tolerance
Error detection, link down and cable open/short diagnostics are common Ethernet fault detection mechanisms, which do provide network management with the ability to identify and locate major faults. These methodologies do reduce downtime, but don't do much to prevent the actual occurrence of network faults. Micrel's Signal Quality Indicator (SQI) addresses this limitation by providing a unique simple 4-bit reading to reflect the receiver signal margin or probability of error.
Benefits are twofold:
•Determine infrastructure cable link quality at installation
•Real-time Link Quality Monitoring: Identifying potential problems prior to errors ensure any potential link issue conditions can be detected and dealt with prior to any catastrophic fault, hence, avoiding network downtime.
An added benefit of the Quiet-WIRE technology discussed above is that enhanced receiver immunity boosts reliability, facilitating error-free traffic over low cost unshielded cables in the harshest environments (See Figure 3).
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Figure 3. Receiver immunity is enhanced with Quiet-WIRE
Transceiver latency considerations for real time, deterministic control networks
Designers must carefully consider Ethernet PHY transceiver latencies when designing real time, deterministic control networks. While reduced latencies are desirable, fixed latency is more critical, as variable delays cannot be compensated in a network, resulting in synchronization jitter.
The basic blocks of the Ethernet PHY architecture are seen in Figure 4a and 4b. In the transmit direction, data is synchronised to the local 25MHz oscillator and typically provides a fixed delay tTX. However, in the receive direction a variable delay is typically exhibited by the locking mechanism of the clock recovery circuitry. This variable delay is due to the alignment, in one of the 5 possible phases: 0ns, 8ns, 16ns, 24ns or 32ns of the generated 25MHz MII RXC clock, with respect to the recovered 125MHz Line Clock. As a result a shift in the receive direction delay occurs every time the link is re-established. This is a common effect, which Micrel has corrected with fixed phase recovered clock mechanism PHY technology.
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Figure 4a and 4b. Fixed PHY latency architecture of the KSZ8061
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Figure 4a and 4b. Fixed PHY latency architecture of the KSZ8061
Safety-critical and real time control applications also benefit from the KSZ8061's ability to power up and link in less than 20ms, without the need for processor intervention.
Looking forward
For the IIoT to become a reality and fulfil its potential there are a number of technological advancements that must be considered, developed and fully implemented. The automotive industry is a good analogy, with Ethernet being adopted in advanced driver assistance systems (ADAS) as the physical bus of choice for camera and sensors. Although digital processing cost in camera and ECU is somewhat higher than traditional analog or LVDS methods, cable costs are considerably reduced by using unshielded cabling. Further, using Power-over-Ethernet (PoE) removes the need for an additional power cable. The ultimate goal is the same, however: delivering a single ubiquitous network seamlessly providing cross-domain communications, even down to devices and sensor layers.
Ethernet stands out as a key enabling technology for all of the reasons outlined above: cost, reliability, performance and power consumption. While there are challenges unique to the IIoT, Ethernet is extremely well positioned to enable this rapidly growing market thanks to its well-established and proven benefits in other markets. Micrel's KSZ8061 PHY family delivers many of the necessary feature attributes needed to enhance Ethernet's ability to perform at device and sensor layers and accelerate the true advent of the IIoT.
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