Author:
Ally Winning, European Editor, PSD
Date
07/05/2022
PDF
The images shows the migration from planar technology, through finFET to GAA
The race between semiconductor manufacturers to get to the next node is always interesting to follow. Samsung beating TSMC to 3nm is pretty big news. This time it is even more relevant as it involves a completely new technology. In previous process nodes, finFET technology was used. This time, the manufacturers have decided to migrate to GAA technology for the transition. FinFET was the first real successful 3D technology and has only really been commercially available over the last decade. As the name suggests, the technology uses fin shaped FETs with the gate surrounding three sides of the channel. The technology provides lower leakage currents, higher drive currents, and faster switching times compared to the previous planar technology. GAAFETs are manufactured with the channel lifted up and the gate enveloping the entire channel. It is a flexible technology that can have a varied channel width to suit the requirements of the transistor type in use. Both finFET and GAA ICs can be designed and manufactured using the same tools and manufacturing techniques.
Samsung’s has named its GAA technology Multi-Bridge-Channel FET (MBCFET). The company claims it overcomes the performance limitations of FinFET, improving power efficiency by reducing the supply voltage level, while improving performance by increasing drive current capability. Samsung implements GAA technology with nanosheets that have wider channels, which allow higher performance and greater energy efficiency compared to GAA technologies using nanowires with narrower channels. The 3nm GAA technology allows Samsung to adjust the channel width of the nanosheet in order to optimize power usage and performance to meet customer needs.
The design flexibility of GAA also helps implement Design Technology Co-Optimization (DTCO), which helps boost Power, Performance and Area (PPA) benefits. Compared to 5nm process, the first-generation 3nm process can reduce power consumption by up to 45%, improve performance by 23% and reduce area by 16% compared to 5nm, while the second-generation 3nm process is to reduce power consumption by up to 50%, improve performance by 30% and reduce area by 35%.
Samsung is starting the first application of the nanosheet transistor with chips for high performance, low power computing applications and in the future will expand its production to mobile processors.
“Samsung has grown rapidly as we continue to demonstrate leadership in applying next-generation technologies to manufacturing, such as foundry industry’s first High-K Metal Gate, FinFET, as well as EUV. We seek to continue this leadership with the world’s first 3nm process with the MBCFET,” said Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics. “We will continue active innovation in competitive technology development and build processes that help expedite achieving maturity of technology.”
Samsung worked on the new process with its partners from the Samsung Advanced Foundry Ecosystem (SAFE), who included Ansys, Cadence, Siemens and Synopsys.
