Powering FPGA Prototyping

I had the pleasure to talk with Doug Amos, Business Development Manager, Solutions Marketing at Synopsys. With 25 years experience in the field of FPGA and ASIC design, Doug has designed or supported countless FPGA and ASIC designs, either as an independent consultant or working with leading vendors. Doug is an expert on FPGA design and FPGA-based prototyping and co-authored the FPGA-based prototyping Methodology Manual (FPMM) in 2011. FPGA prototyping has been the mainstay for SoC designs for many years. The tools required to optimize partitioning, power and performance, although complex in their make-up, are becoming much easier to use. The main benefit is in verifying the HW and SW together, well in advance of the first SoC silicon becoming available. "With the high probability of a SoC finding its way into consumer devices such as cell-phones or other portable applications, the power aspects are a major consideration. Prototyping in FPGAs is a vital part of the development of the final chip. Prototypers see their goal as ‘interfacing with the real world'. When the first silicon comes back for test and evaluation, this is not the time to start wondering where things went wrong," Doug explained, summarizing the traditional challenges in prototyping in the following ‘three laws of prototyping': 1. SoCs are larger than FPGAs 2. SoCs are faster than FPGAs 3. SoCs designs are FPGA-hostile The many and powerful ways that prototypers overcome these challenges are described in the FPMM, which is available by download from the FPMM website. With the best tools, boards, devices and IP available today, even the most daunting SoC design can be converted into a good, working FPGA prototype, but this is seen by Synopsys as the minimum requirement. Traditionally SoC designers and FPGA prototypers have been looked at as two separate entities, and yet an optimized outcome can only be achieved when all are working towards the same goal. This is called Design-for-Prototyping. Much more can be done by using a Design-for-Prototyping approach to smooth the way through a SoC project, not least in making the SoC design more FPGA-prototyping-friendly in the first place. This can save weeks or even months in the design cycle and translates directly into revenue for the design house. Whereas a silicon provider can provide the best fit process and geometry, including libraries that trade-off between power and performance, users can also use advanced techniques such as clock frequency scaling and dynamic voltage scaling. The FPGA prototype, however, is more focussed on the functionality of the design and reaching the performance needed to allow the software run in real-time. The tools at the FPGA prototyper's disposal, such as Certify prototyping tools from Synopsys, can aid the fast delivery of a prototype that already has some of the power-mitigation techniques included. Many of these mitigation functions, such as Gated Clock Conversion and manipulation which would otherwise be a laborious task for the FPGA prototyper, are now completely automated in the tools now available. In the end, the sooner prototypers can provide a working system, the sooner the HW and SW verification can be completed; Today, the software content is the critical path item, so the time saving factor again, adds to the ‘bottom line'. This is just a snapshot of what I could cover with Doug. It is a vital and interesting area in our industry and PSD will go deeper into this in forthcoming issues. From my perspective I was grateful for Doug's explanations and for the copy of the FPMM that I have as reference. www.synopsys.com