OpenTitan Partnership Makes History as First Open-Source Silicon Project to Reach Commercial Availability

­lowRISC C.I.C., the open silicon ecosystem organization, and the OpenTitan coalition today announced a historic milestone as the first open-source silicon project to reach commercial availability, with validated chips in hand. The capstone moment is the result of an unprecedented amount of support and investment by the nine coalition members, including Google, Winbond, Nuvoton, zeroRISC, Rivos, Western Digital, Seagate, ETH Zurich and Giesecke+Devrient, hosted by the non-profit lowRISC CIC.

“I am incredibly proud of the OpenTitan partnership for succeeding where every other project has failed – producing the first commercial quality open-source chip in the world,” said Dr. Gavin Ferris, CEO of lowRISC, OpenTitan’s host organization. “This is the culmination of the monumentally hard work of a vibrant and engaged community of contributors focused on a singular goal to achieve what’s never been done before – make open-source silicon work the same way as open-source software. I am grateful for this support and can’t wait for what’s to come.”

Google launched the OpenTitan project together with lowRISC and its partners in 2018 with the goal to make a completely transparent and trustworthy secure silicon platform. It is the world’s first open-source secure chip to include commercial-grade design verification, top-level testing and continuous integration. Capable of serving as the hardware root of trust, OpenTitan ensures that the hardware infrastructure and the software that runs on it remain in their intended, trustworthy state by verifying that the critical system components boot securely using only authorized and verifiable code.

With Google’s support, the project took off from its first year, setting it on a trajectory to make it the most active and successful open-source silicon project in history. Throughout its lifetime, the OpenTitan coalition thrived as an open silicon ecosystem, consistently following a well-defined roadmap from discrete to integrated secure silicon designs. The project partners are deeply engaged in this process, ensuring that the final designs are adaptable to many applications. OpenTitan also has a large and growing community of contributors beyond its formal partners. As a whole, the community resolves hundreds of pull requests and issues monthly.

“OpenTitan in silicon is the realization of many years of dedication and hard work from our team. It is a significant moment for us and all contributors to the project,” emphasized Miguel Osorio, OpenTitan Lead at Google.

This major milestone follows a series of significant successes for the OpenTitan project in 2023. Most critically, the project also accomplished the first discrete silicon tapeout in June 2023. In November 2023, the project coalition announced the first SoC secure execution environment, including RoT functionality, which has enabled coalition partners to embed OpenTitan in their SoC and chiplet designs.

Supporting Quotes from OpenTitan Members

“We’ve been privileged to work closely with our OpenTitan coalition partners from early on and are even prouder now to bring the first ‘EarlGrey’ OpenTitan chip design to market, demonstrating our leadership in open, secure ICs,” said Erez Naory, VP of Client and Security Products at Nuvoton. “Open-source secure silicon is now proven as a radical leap forward in solving the market’s need for a truly trustworthy foundation.”

“Our mission is to advance the incredible work of the OpenTitan project by delivering an end-to-end supply chain security solution built on an open secure silicon foundation,” said Dom Rizzo, zeroRISC CEO. “That we’re able to deliver commercial products so soon after tapeout clearly illustrates the coalition’s momentum. With this first, crucial step for open silicon implementations, we look forward to a world where a transparent and trustworthy supply chain is the default.”

“The rigor at the heart of the OpenTitan project’s roadmap has ensured the success of this first-of-its-kind, silicon-proven integrated design,” said Tung-Yi Chan, Vice Chairman and Deputy CEO at Winbond. “By proving the viability of securely integrating certified IPs, OpenTitan opens up new possibilities for SoC vendors. Winbond supports the OpenTitan initiative with its certified Secure Flash solutions.”

“We’ve benefited tremendously from the collaborative relationships within the OpenTitan partnership,” said Mark Hayter, Founder and Chief Strategy Officer of Rivos Inc. “It’s made it easy for us to share our SoC experience to help the coalition provide silicon-proven IP that enables us to integrate RoT into our chiplets.”

“Seagate is a proud consortium member and contributor of the OpenTitan project,” according to Ed Gage, VP of Seagate Research. “Both the open-source IP and the OpenTitan chip will set a new baseline for hardware-based security. Seagate considers this high-quality security IP a key enabler of both enhanced storage device integrity and data protection.”

“It has been a privilege for Giesecke+Devrient to contribute to the success of OpenTitan so far, as we believe that a secure IP block based on OpenTitan will enable smooth, fast and cost-effective integration into larger SoCs, unlocking a host of new use cases, especially in the IoT ecosystem,” says Bernd Müller, Head of Connectivity and IoT Portfolio Strategy at Giesecke+Devrient. “With G+D's trusted embedded operating systems pre-integrated on OpenTitan coupled with our broad portfolio of IoT and connectivity solutions, we are excited for the opportunity this provides us to support customers and projects in this emerging ecosystem.”

The OpenTitan coalition continues to work in unison to accelerate the project’s momentum. Upcoming key milestones include the full production release of the “Darjeeling” integrated OpenTitan secure extension environment (SEE) and the first production release of “Chai,” the integrated OpenTitan SEE with support for secure external flash. In addition, the project will release an updated discrete “EarlGrey” chip design, with additional coverage and development.