Maximize SiC MOSFET Performance with Optimized Gate Drivers

­Silicon MOSFETs and IGBTs have traditionally dominated the market for power electronic applications such as uninterruptible power supplies, industrial drives and pumps and electric vehicles (EVs). Market demand for smaller form-factors however, along with various pressures on designers to improve power efficiencies, has seen the emergence of Silicon Carbide (SiC) MOSFETs as a popular alternative these applications.

As with Silicon MOSFETs, the operational characteristics and performance of SiC MOSFETs are dependent on the design of the gate driver circuit, which is responsible for turning the device on and off. The specific characteristics of SiC, however, dictate careful selection of both the MOSFET device and gate driver circuit to ensure that the requirements of the application are safely met, and efficiencies are maximized.

Efficiency in Power Electronics Design 

Power electronics systems can process substantial amounts of electrical energy, ranging up to tens of megawatts, and the design of electrical power applications in today’s market is increasingly driven by efficiency requirements along with the demands of regulation. Current density and efficiency are key enablers of the smaller form factors demanded by the market, since higher efficiencies lead to lower power losses, with a consequent reduction in the need for cooling solutions on PCBs and enclosures. 

Efficiencies are also coming under increasing scrutiny as emissions regulations tighten. MOSFETs, for example, are key components of the power drive systems (PDS), which drive electric motors. In Europe alone, the European Commission estimates that there are around eight billion electric motors in use, which consume almost half of all the electrical energy generated in the region. The electrical efficiency of these devices is therefore, unsurprisingly, subject to increasingly strict regulatory requirements.

SiC MOSFETs, when properly implemented, offer important advantages in power density and efficiency. The more compact SiC components, with their higher switching frequencies, enable a reduction in overall system size, with obvious benefits in space and weight sensitive applications such as EVs. In order to achieve the potential benefits of SiC MOSFETS, however, the device must be suited to the specific demands of the application by carefully choosing an appropriate gate driver.

SiC MOSFET Characteristics

System size and electrical efficiency are critical requirements of many modern power electronic systems, and SiC has emerged as a popular semiconductor technology. As a wide bandgap material, SiC has numerous advantages over silicon, including high thermal conductivity, low thermal expansion coefficient, high maximum current density, and superior electrical conductivity. Additionally, SiC’s low switching losses and high operating frequencies offer enhanced efficiencies, particularly in applications which require high current, high temperatures, and high thermal conductivity.

With voltage thresholds into 10s of kV, compared with 900 V for Si, and higher critical breakdown fields, the reduced thickness of SiC devices can support higher given voltage ratings. 

When properly implemented, SiC devices can offer the designer important advantages in efficiencies and switching frequencies, and the more compact SiC components enable a reduction in overall system size. These benefits are extremely useful in space and weight sensitive applications such as EVs, Rail transport or Energy Infrastructure. As SiC technology advances to withstand higher voltages, enabling devices rated at 1700V and above, its superiority over traditional silicon will become even more pronounced. 

SiC MOSFET Gate Driver Design Considerations

The design of the gate driver ensures the safe operation of the MOSFETs used in the power application. Factors to be considered when choosing a gate driver include:

● Miller Capacitance (C_DG) and Parasitic Turn On (PTO)

SiC MOSFETs are prone to parasitic turn on (PTO), due to the Miller capacitance, C_DG, which couples the drain voltage to the gate during switching events. As the drain voltage rises, this coupled voltage can briefly exceed the gate threshold turning the MOSFET on. MOSFETs are often paired in circuits such as synchronous buck converters, which have a high side and a low side MOSFET, and PTO can lead to shoot-through conduction in these circuits. Shoot-through conduction occurs when both high side and low side MOSFETs are simultaneously switched on, resulting in the high voltage shorting to GND, through both MOSFETs. The severity of this shoot-through depends on the operating conditions of the MOSFET and the design of the gate circuit, with critical factors including bus voltage, switching speed, (dv/dt) and drain-source resistance, (R_DS(ON)). In the worst case, PTO can trigger disastrous results, including short-circuits and damage to the MOSFET.

PTO can also be compounded by parasitic capacitances and inductances related to PCB layout and packaging. This can be avoided by negatively biasing the turn-off voltage of the device, as discussed below.

● Gate Driver Voltage Range

A MOSFET is turned on and off by the application of a voltage to its gate terminal, supplied by a dedicated gate driver, Figure 1. The gate driver is responsible for sourcing the current which charges the gate of the MOSFET up to its final turn-on voltage, V_GS(ON), and also for sinking the current as the device is discharged to its final turn−off voltage, V_GS(OFF). 

The positive voltage of the gate drive should be high enough to fully turn the MOSFET on while, at the same time, not exceeding the maximum gate voltage. When working with SiC MOSFETs, it is important to consider that they usually require higher gate voltages than Silicon MOSFETs. Equally, whereas 0 V is sufficient to ensure turn-off of Si MOSFETs, a negative bias is generally recommended for SiC devices to eliminate the risk of parasitic turn on. Allowing the voltage to swing down to -3 V or even -5 V during turn off creates some headroom or margin against the conditions which can trigger V_GS(TH) and accidentally turn the device on.

Negatively biasing the gate voltage in this way has the additional benefit of reducing E_OFF losses in the MOSFET. By lowering the turn-off voltage from 0 V to -3 V when driving onsemi’s Gen 2 “EliteSiC M3S” series of SiC MOSFETs, E_OFF losses were reduced by 25%, as shown in Figure 2.

Click image to enlarge

Figure 2: Negative Gate Bias (Source: AND90204/D)

● R_DS(ON) and Q_G(TOT), Total Gate Charge

R_DS(ON) is the resistance between the drain and the source of the MOSFET when the device is turned on by a specific gate-to-source voltage (VGS) applied to the gate. As V_GS increases, R_DS(ON) usually decreases and, in general, the lower the R_DS(ON), the better, since the MOSFET is being used as a switch. The Total Gate Charge Q_G(TOT) is the electrical charge, in coulombs, required to turn the MOSFET fully on, and is typically inversely proportional to R_DS(ON). Q_G(TOT) charge is supplied by the gate driver and so the driver must be capable of sourcing and sinking the required current.

Optimizing Power Losses 

Achieving reduced switching losses with SiC MOSFETs requires the designer to be conscious of several trade-offs. The total power loss of a SiC MOSFET is the sum of its conduction losses and its switching losses. Conduction losses, which are essentially calculated as I_D^2*R_DS(ON), where I_D is the drain current, can be minimized by choosing devices with low R_DS(ON). However, lower R_DS(ON) values require the gate driver to source and sink higher current levels due to the inverse relationship between Q_G(TOT) and R_DS(ON) described above. In other words, as designers select lower R_DS(ON) SiC MOSFETs to reduce conduction losses in their high-power applications, the gate drive source (turn on) and sink (turn off) current requirements increase proportionally. 

The switching losses of a SiC MOSFET are more complicated, since they are influenced by device parameters such as Q_G(TOT), Reverse Recovery Charge (Q_RR), Input Capacitance (C_ISS), Gate Resistance (R_G), E_ON losses and E_OFF losses. Switching losses can be reduced by increasing the switching speed of the gate current, but, at the same time, faster switching speeds can introduce unwanted electromagnetic interference (EMI), and can also trigger PTO, during intended switch turn off, especially in half bridge topologies. Switching losses can also be reduced by negatively biasing the gate voltage, as discussed above.

Example of a Gate Driver

Gate driver design is therefore critical to ensure that the SiC MOSFETs in a power electronics application function as intended. Fortunately, a wide range of purpose-built gate driver ICs is available on the market from manufacturers such as onsemi, abstracting the designer from the details of driver circuit engineering – and saving BoM costs and PCB real-estate.

The NCP(V)51752 family of isolated SiC gate drivers, for example, are designed for the fast switching of power MOSFET and SiC MOSFET devices, offering source and sink currents of 4.5 A and 9 A respectively. The NCP(V)51752 family includes an innovative embedded negative bias rail mechanism, avoiding the need for the system to supply a negative bias rail to the driver, saving design effort and system costs. 

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