Enhancing Speed and Efficiency for High Transient Automotive Applications

­High current, low voltage applications frequently employ a multiphase buck converter topology for the voltage step down. This multiphase buck can utilize traditional discrete inductors (DL), as shown in Figure 1a, or coupled inductors (CL), as depicted in Figure 1b. In the case of CL, the windings are magnetically coupled, providing the advantage of current ripple cancellation.

Automotive ADAS applications face a challenge in maintaining tight regulation for GPU or ASIC rails within the 0.4 V to 1 V range, especially under fast transient conditions. A loading transient generally causes all phases to turn the switching nodes V_X high to V_IN, so the inductor current in each phase ramps up with a slew rate (1), where V_IN is input voltage, V_o is output voltage, and L is inductance value. An unloading transient typically causes all phases to turn low to GND and the inductor current ramps down (2). Given the low output voltage value V_OUT <1V and assuming that the input voltage is typically 5V or even higher, it is easy to see from the comparison of equations 1 and 2 that the unloading transient creates the main problem as there is only a small voltage to ramp the current down.

The simple solution involves increasing the number of ceramic output capacitors in C_OUT. However, the size and cost of this approach can swiftly become impractical. In the automotive industry, voltage regulators are often configured to switch at a relatively higher frequency (F_S), typically exceeding 2MHz. This is in contrast to regulators in cloud or industrial applications. The higher switching frequency is necessary in automotive settings due to specific electromagnetic interference (EMI) requirements. While this choice helps to decrease inductance values in the regulator, further enhancements are still required.

The current ripple in each phase of the conventional buck with DL can be found as Equation 3, where the duty cycle is D=V_OUT/V_IN, V_OUT is the output voltage, V_IN is the input voltage, L is inductance value, and F_S is the switching frequency.

Replacing the DL with CL that has a leakage inductance L_K and the mutual inductance L_M, the current ripple in CL can be shown as Equation 4. The term  defined as figure of merit (FOM) is expressed as Equation 5, where N_PH is the number of coupled phases, ρ is a coupling coefficient (Equation 6), and j is a running index, which just defines an applicable interval of the duty cycle (Equation 7). The parameters of the CL are the leakage inductance L_K and the mutual inductance L_M.

The meaning of FOM in equations 4 and 5 for the particular CL design can be interpreted as an additional multiplier in current ripple cancellation as compared to the conventional buck with discrete inductor L. The definition of FOM and its meaning were also generalized and extended11to compare any systems with arbitrary current ripple and transient performances. The proposal is to use a ratio of the normalized transient spew rate (desired high) to the normalized current ripple (desired low) (Equation 8). The transient slew rate and the current ripple are normalized by related numbers for some benchmark converters with discrete inductors (so any system with DL will still lead to FOM = 1). The SRTR and ΔIL are transient current slew rate and current ripple in a steady state of the chosen design or technology, while SRTR_DL and ΔILDL are the same parameters but for the benchmark DL design.

Equation 8 can be simplified into Equation 9, using the fact that the current slew rate for the discrete inductor is the same in transient and steady state. This way, any actual reference to DL design is completely removed, while the benchmarking ideology is still there.

Notice that using the generalized FOM definition, Equation 9, for the CL will result in Equation 5, so the new definition is backward compatible, but can also be used for technologies where both current ripple and transient slew rate are arbitrarily different from the DL equations (for example, TLVR9).

CL Design and Considerations

The application specifications are V_IN = 5V, V_OUT = 0.8V, F_S = 2.1 MHz, and N_PH = 8. As a starting point, DL = 32nH is chosen to support the fast transient, while each inductor occupies 4.2 mm × 4.2 mm × 4.2 mm. Ideally, these would be substituted with an 8-phase coupled inductor (CL). However, the low height requirement of h = 4 mm presents a challenge, as it would make such a lengthy componentun manufacturable due to being excessively thin and long, while also increasing sensitivity to board flex. Therefore, the 4-phase building block was chosen for CL. This also enables better flexibility with placement and layout. As the faster transient is targeted and knowing that the CL will have smaller ripple than the starting DL value, the recently introduced Notch CL (NCL) structure was proposed to minimize the leakage value L_K.7,8,10 The NCL0804 was designed with L_K~17nH and OCL=L_M+L_K = 100nH, N_PH = 4, phase pitch 6.9mm/phase, and a height h = 4.0 mm max.

A good way to compare different designs is a FOM plot.¹⁰ Any DL design will have FOM = 1, as the trade-off between the current slew rates in steady state and transient is 1:1. The NCL structure of the coupled inductor maximizes LM/LK ratio in a given size, so it generally results in the highest FOM.⁹ The FOM comparison is shown in Figure 2, where the developed NCL is ~4.4× better than DL around the targeted output voltage.

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The corresponding current ripple comparison is shown in Figure 3 and Table 1.While the DL value can be chosen in a wide range for a different compromise between current ripple and transient slew rate, the advantage of developed NCL is always 4.4×. This correlates to 2.35 × smaller current ripple than the ripple of DL = 32nH while NCL is 1.88 × faster. Then 2.35 × 1.88~4.4, matching the predicted FOM = 4.4. The current ripple can also be lowered a lot by using DL=100nH, which makes it 1.33× smaller current ripple than that in NCL, but NCL is then 5.88× faster, resulting in the same 5.88/1.33~4.4× advantage of NCL over any DL (FOM= 4.4 for NCL).

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Looking at a theoretical FOM for the same NCL in Figure 2 but considering if N_PH = 8 is manufacturable: the performance advantage of NCL over DL would increase from 4.4× to 5.8×, and make even more relative difference at a lower V_OUT.

Looking ahead, it might be worth considering a different design for the NCL. One possibility is arranging the phases in two rows to maintain a low aspect ratio (length/height) of the ferrite core, making it conducive to manufacturing. In this scenario, the NCL could potentially be positioned at the bottom of the PCB, directly above the ceramic bypass for the GPU, with power stages surrounding the NCL on the perimeter. The approach, akin to a vertical power delivery (VPD) arrangement, could potentially enhance the trade-off between transient and ripple (effectively transient efficiency). However, it’s crucial to note that implementing such achange would be a significant departure from the existing design and layout. Whether this proposed approach is considered in the future will depend on customer preferences.

Experimental Results

Substituting the DL = 32 H inductors with NCL0804-4 resulted in enhanced efficiency, as shown in Figure 4. This improvement is mainly attributed to the significant reduction in current ripple (Figure 3), leading to lower rms currents in windings, power stages, and traces. Additionally, it contributes to lower AC losses, as depicted in Figure 4.

At the same time, the 17 nH/phase NCL offers ~1.9× faster current slew rate in transient and generally improves the phase margin in the feedback loop. Stepping down on ripple with DL=100nH recovers the efficiency, Figure 4, but such DL is significantly taller than the allowed h=4mm height, while also being ~5.9× slower than developed NCL. The latter would cause extreme implications for the amount of needed output capacitors. The results confirm the fundamental performance advantage of NCL as expected from the FOM estimates, against the different trade-off options of the discrete inductor approach.

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