Docea Power to show the latest Aceplorer and Thermal Profiler software tools at the 52nd Design Automation Conference
Docea Power, a provider of virtual prototyping solutions for power and thermal, will reveal at the 52nd Design Automation Conference (DAC) the latest releases of its Aceplorer and Thermal Profiler software tools. Docea Power will demonstrate new advances in power and thermal management modeling and simulation with Aceplorer 4.0 and Thermal Profiler 4.0 new solvers to speed up thermal verification.
Aceplorer 4.0 features a new programming interface, the PTM-API (Power and Thermal Management Application Programming Interface) for modeling complex power and thermal management algorithms (e.g. Android Governors, CPUFreq, CPUIdle). This feature enables to simulate the performance of a chipset given a specific power management policy.
The PTM-API is useful:
- For extensive what if analysis, to explore new power management policies effectiveness
- To optimize current power management software
- To speed up validation of power management software.
A major issue for chipset vendors and OEMs is to predict the real performance of their devices on a thermally constrained environment. In many devices (e.g. mobile chipsets, automotive ICs), high performance modes can only be sustained for a limited time. The real devices’ performance is the result of a mix between high speed and low power modes. This mechanism is called thermal mitigation (or throttling) and must be characterized and optimized. Docea Power provides unique solutions for thermal throttling modeling and simulation thanks to compact thermal models generated by the Thermal Profiler, Aceplorer coupled power and thermal simulator and the new PTM-API to model power and thermal management policies.
The Thermal Profiler 4.0 release is augmented with new steady state and step response solvers that facilitate the validation of thermal models imported from CFD tools before generating a compact thermal model for fast dynamic simulations.
In addition, Docea Power solutions will be presented in the following events during the conference:
DESIGNER AND IP TRACK Presentation:
Session 25. INNOVATIVE FRONT-END DESIGN AND VALIDATION AT SYSTEM LEVEL.
25.1 Enabling Efficient Validation of Temperature-Dependent System Behavior Through Co-Emulation
Speaker: Tanguy Sassolas, CEA LETI, Gif-sur-Yvette, France
When & where: TUESDAY June 09, 1:30pm - 3:00pm | Room 105
DESIGNER AND IP TRACK POSTER: Interactive presentations:
31.36 System Level Thermal Analysis Platform for Mobile SoC
Speaker: Wook Kim - Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
When & where: TUESDAY June 09, 4:30pm - 6:00pm | Exhibit Floor
31.69 Architectural Trade-Off Analysis
Speaker: Minyoung Mo - Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
When & where: TUESDAY June 09, 4:30pm - 6:00pm | Exhibit Floor
When/Where
Monday-Tuesday, June 8-9, 2015, 10 am to 7 pm
Wednesday, June 10, 2015, 10 am to 6 pm
Docea Booth #3507
Moscone Convention Center, San Francisco, CA
