Author:
Hubert Baierl, Director of Product Marketing, Infineon Technologies
Date
04/20/2023
PDF
Courtesy of Infineon
Safely achieving increasingly higher power densities in compact form factors is among the goals for today’s switch mode power supply (SMPS) designs used in industrial and other applications. To meet these goals, all aspects of the design must be considered. This includes: a totem-pole power factor correction (PFC) stage, high-voltage, half-bridge LLC stage, full digital control, integrated planar magnetics and advanced gate-driver ICs. Taking all of these factors into account, a 3.3-kW switch mode power supply with 98% efficiency, in 1U form factor and a power density of 100 W/in.3 can be achieved. Advanced gate driver ICs play a critical role in the design. Before presenting specific attributes of recently introduced gate driver ICs, industry standards to ensure safety will be reviewed.
MEETING REGULATORY SAFETY REQUIREMENTS
Industrial applications frequently involve regional government regulations to ensure the safety of operators and equipment. In North America, safety requirements are typically specified by Underwriters Laboratories (UL), American National Standards Institute (ANSI) and Canadian Standards Association (CSA). In Europe and beyond, the International Electrotechnical Commission (IEC) and Deutsches Institut für Normung (DIN) and Verband der Elektrotechnik, (VDE) address safety standards.
As shown in Table 1, VDE 0884-11 (and the IEC 60747-17) requirements are the strictest for specifying input-output isolation and could be called the gold standard of safety requirements. Primarily based on partial discharge rather than breakdown testing, VDE certifications include isolation voltage (VISO), transient overvoltage (VIOTM), and minimum surge isolation voltage (VIOSM) or surge immunity that other standards specify as well.
By requiring time-dependent dielectric breakdown (TDDB) testing to determine the rated peak repetitive voltage (VIORM), VDE 0884-11 identifies (for the first time) a 20-year application time. The voltage safety factor of 1.2 (20% higher voltage requirement) becomes 1.3 for basic isolation and 1.875 reinforced isolation certification for lifetime safety factors. As a result, obtaining VDE or IEC standard certification is important and even essential in many industrial applications.
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Table 1. Component-level isolation standards overview
1) Time Dependent Dielectric Breakdown
Additional safety requirements for creepage, clearance and pollution degree, such as those in IEC 60664-1, may be required in some applications. Isolation techniques to meet various safety requirements include optical, capacitive and magnetic as well as galvanic isolation. Figure 1 shows inductive galvanic isolation.
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Figure 1: Galvanic isolation on the input side (left) and magnetic (transformer based) input to output isolation (right) allow gate driver ICs to meet VDE 0884-11 and other isolation standards
PROVIDING HIGHER PROTECTION WITH SAFETY
In addition to meeting safety requirements, increased protection is also required for the latest power designs to ensure long system life. Undervoltage lockout (UVLO) output-stage startup time, UVLO shutdown time, output clamping, other protective circuitry and packaging can differentiate one gate drive design from the competition. Based on magnetically coupled coreless transformer (CT) technology, which provides signal transfer across the galvanic isolation, EiceDRIVER™ isolated gate drivers are certified to meet VDE 0884-11 and provide these capabilities and more. The recently introduced 2EDR8259 dual-channel galvanic isolated gate-driver will be used to explain these improvements.
Optimizing UVLO Output-Stage Startup Time
Different options exist for driving the gates of high-side (HS) switches however, the bootstrap approach is the most common, cost-effective solution. In these designs, a short start-up time provides fast normal system operation, short LLC start-up after brown-outs or restarts and no mains-power-transformer saturation due to asymmetric high-side versus low-side pulse-width modulation (PWM) operation during the ramp-up of the bootstrap supply.
When using dual-channel galvanic isolated gate-driver ICs with 2-μs typical UVLO startup time in a bootstrapped high-side configuration, only four high-side pulses are skipped until the half-bridge starts operating (provided the VDD increase of the high-side is what is deemed to be typical). A similar gate-driver IC with a UVLO startup time of 10 μs or more easily can lead to skipping of 9 or more high-side pulses. This significantly delays the start of the half-bridge operation.
Actual measurements of the recently introduced dual-channel isolated gate-driver IC with less than 2-μs compared to a competitive design with approximately 10-μs are shown in Figure 2.
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Figure 2: UVLO startup time comparison of state-of-the-art dual-channel isolated gate-driver ICs
Optimizing UVLO Shutdown Time
The primary objective of UVLO-triggered output-stage shutdown is to be fast enough to protect the switching device from thermal overload. However, if only an intermittent drop below the UVLOoff threshold occurs, the switching stage should not be turned off. Practical experience shows that a shutdown delay of 500 ns is sufficient to avoid that noise or ringing on VDD could initiate an undesired output-stage shutdown.
Output Clamping
Output clamping ensures that the output stage is safely off while the gate-driver supply is still below the UVLOon threshold. Proper clamping reduces the risk of shoot-through during the bootstrapped startup of half-bridges. When the supply is above the UVLOon threshold, the gate-driver IC is expected to propagate the control input to the output stage. Since the output is no longer clamped, it follows the input signal.
In a bootstrapped half-bridge stage, when the low-side is switching to charge the boost capacitor, the capacitive voltage divider consisting of CGD and CGS of the high-side switch causes an increase of VGS over its on-threshold. Proper gate-driver IC output clamping avoids VGS exceeding this on-threshold by short-circuiting (“clamping”) the output. If output clamping does not occur in a timely manner, the high-side switch turns on simultaneously with the low-side, creating a half-bridge shoot-through.
Figure 3 shows an active output-clamping circuit that becomes effective at VDD levels as low as 1.2 V. In contrast, if a gate-driver IC has a slow internal RC clamping circuit, a certain level of shoot-through occurs during the startup of the half-bridge until VDD is eventually high enough to activate the output-clamping circuitry. This shoot-through is undesirable because it leads to electrical overstress (EOS) for the switching devices.
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Figure 3: An active output clamp acts faster than an output stage with a passive, internal RC clamp to avoid/minimize EOS on switching devices
Shoot-through Protection
Shoot-through protection ensures deadtime in half-bridges that allows the switch’s tail current to decay after the switch has been turned off and prior to the other side of the half-bridge being turned on. In addition to software-controlled deadtimes that are typically not shorter than 300 ns, the newest dual-channel isolated gate driver ICs offer a configurable deadtime setting through an external resistor. With selectable deadtimes ranging from as short as 10 ns to as long as 1,000 ns, the gate-driver ICs are very versatile for a range of power-switch technologies, including GaN power switches. The accuracy of this deadtime can be as good as ±15%. This approach is frequently substantially more precise than the actual control IC-based deadtime control.
New Packaging Options
Dual-channel galvanic isolated gate-driver ICs in 150- and 300-mil DSO packages are available in a 14-pin configuration. Instead of using a 16-pin package with two “no connect” pins between the two output channels, a 14-pin configuration enables additional printed circuit board (PCB) top-level routing options. (See Figure 4.) Since the resultant channel-to-channel creepage distance is increased to 3.4 mm, the 14-pin version permits a channel-to-channel functional isolation voltage of up to 1,025 VRMS (referring to IEC 60664-1, Pollution Class I).
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Figure 4: The 14-pin version of a 16-pin DSO package provides several benefits for isolated gate-driver ICs
Dual-channel low-side gate-driver ICs with six-pin packages, such as leaded SOT-23 (Figure 5 right) or eight-pin packages (Figure 5 left) can provide flexibility and cost-effective alternatives. With the right choice, PCB area consumption is minimized and PCB layout flexibility is achieved.
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Figure 5. Examples of dual-channel low-side gate-driver ICs in small-form–factor for design options.
The Need for Higher Isolation and Improved Protection
With advanced safety capabilities certified to meet the most stringent VDE 0884-11 and IEC 60747-17 isolation standards, system designers can focus on other critical performance and protection circuitry. The newest isolated gate drivers coupled with existing dual-channel low-side gate-driver ICs satisfy these design requirements. The combination of attributes avoids premature device failures and provides systems increased ruggedness for a much-extended useful life. In addition to the servers used to store and coordinate the operation of machines and factory processes, machine tool products, robots and cobots can also benefit from improved safety and protection from dual-channel isolated gate driver ICs.
